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1 of 11 rev: 060706 features integrated nv sram, real-time clock, crystal, power-fail control circuit, and lithium energy source standard jedec bytewide 2k x 8 static ram pinout clock registers are accessed identically to the static ram. these registers are resident in the eight top ram locations totally nonvolatile wi th over 10 years of operation in the absence of power access times of 70ns and 100ns quartz accuracy 1 minute a month at +25c, factory calibrated bcd-coded year, month, date, day, hours, minutes, and seconds with leap year compensation valid up to 2100 power-fail write protection allows for 10% v cc power supply tolerance lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ul recognized pin configuration ordering information part voltage range (v) temp range pin-package top mark DS1642-70+ 5.0 0c to +70c 24 edip (0.720a) ds1642+70 DS1642-70 5.0 0c to +70c 24 edip (0.720a) DS1642-70 ds1642-100+ 5.0 0c to +70c 24 edip (0.720a) ds1642+100 ds1642-100 5.0 0c to +70c 24 edip (0.720a) ds1642-100 *ds9034-pcx, ds9034i-pcx, ds9034-pcx+ required (must be ordered separately). a ?+" indicates a lead-free product. the top mark will include a ?+? symbol on lead-free devices. ds1642 nonvolatile timekeeping ram www.maxim-ic.com v cc a8 a9 w e o e a10 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq0 dq1 dq2 gnd c e dq7 dq6 dq5 dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ds1642 encapsulated dip top view
ds1642 2 of 12 pin description pin name function 1 a7 2 a6 3 a5 4 a4 5 a3 6 a2 7 a1 8 a0 19 a10 22 a9 23 a8 address input 9 dq0 10 dq1 11 dq2 13 dq3 14 dq4 15 dq5 16 dq6 17 dq7 data input/output 12 gnd ground 18 ce active-low chip-enable input 20 oe active-low output-enable input 21 we active-low write-enable input 24 v cc power-supply input description the ds1642 is a 2k x 8 nonvolatile static ram and a fu ll-function real-time cloc k (rtc), both of which are accessible in a bytewide format. the nonvolatile time keeping ram is pin and function equivalent to any jedec-standard 2k x 8 sram. the device can also be easily substituted in rom, eprom, and eeprom sockets, providing read/write nonvolatility and the addition of the real -time clock function. the real-time clock information resides in the eight uppermost ram locations. the rtc registers contain year, month, date, day, hours, minutes, and seconds da ta in 24-hour bcd format. corrections for the day of the month and leap year are made automatically . the rtc clock registers are double-buffered to avoid access of incorrect data that can occur during cl ock update cycles. the double-buffered system also prevents time loss as the timekeeping countdown conti nues unabated by access to time register data. the ds1642 also contains its own power-fail circu itry, which deselects the device when the v cc supply is in an out-of-tolerance condition. this feature prevents loss of data from unpredictable system operation brought on by low v cc as errant access and update cycles are avoided.
ds1642 3 of 12 clock operations?reading the clock while the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the ds1642 clock registers should be halted before clock data is read to prevent reading of data in transition. however, halting the internal clock regist er updating process does not affect clock accuracy. updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register. as long as a 1 remains in that position, updating is ha lted. after a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt co mmand was issued. however, the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. all of the ds1 642 registers are updated simu ltaneously after the clock status is reset. updating occurs within a second after the read bit is written to 0. figure 1. ds1642 block diagram table 1. truth table v cc ce oe we mode dq power v ih x x deselect high-z standby v il x v il write data in active v il v il v ih read data out active 5v 10% v il v ih v ih read high-z active <4.5v > v bat x x x deselect high-z cmos standby ds1642 4 of 12 setting the clock the 8th bit of the control register is the write bit. setting the write bit to a 1, like the read bit, halts updates to the ds1642 registers. the user can then load them with the correct day, date and time data in 24-hour bcd format. resetting the write bit to a 0 then transfers those values to the actual clock counters and allows normal ope ration to resume. stopping and starting the clock oscillator the clock oscillator may be stopped at any time. to incr ease the shelf life, the oscillator can be turned off to minimize current drain from the battery. the osc bit is the msb for the seconds registers. setting it to a 1 stops the oscillator. frequency test bit bit 6 of the day byte is the frequency test bit. when the frequency test bit is set to logic 1 and the oscillator is running, the lsb of the seconds register will toggle at 512 hz. when the seconds register is being read, the dq0 line will toggle at the 512 hz freque ncy as long as conditions for access remain valid (i.e., ce low, and oe low) and address for seconds re gister remain valid and stable. clock accuracy the ds1642 is guaranteed to keep time accuracy to within 1 minute per month at 25 c. dallas semiconductor calibrates the clock at the factory by using special calibration nonvolatile-tuning elements. the ds1642 does not require additiona l calibration and temperature devi ations will have a negligible effect in most applications. for this reason, methods of field clock calibration are not available and not necessary. table 2. register map?bank1 data address b7 b6 b5 b4 b3 b2 b1 b0 function 7ff ? ? ? ? ? ? ? ? year 00?99 7fe x x x ? ? ? ? ? month 01?12 7fd x x ? ? ? ? ? ? date 01?31 7fc x ft x x x ? ? ? day 00?23 7fb x x ? ? ? ? ? ? hour 00?59 7fa x ? ? ? ? ? ? ? minutes 00?59 7f9 osc ? ? ? ? ? ? ? seconds 00?59 7f8 w r x x x x x x control a osc = stop bit r = read bit ft = frequency test w = write bit x = unused note: all indicated ?x? bits are not used but must be set to ?0? during write cycle to ensure proper clock operation.
ds1642 5 of 12 retrieving data from ram or clock the ds1642 is in the read mode whenever we (write enable) is high, and ce (chip enable) is low. the device architecture allows ripple-through access to any of the address locations in the nv sram. valid data will be available at the dq pins within t aa after the last address input is stable, providing that the ce and oe access times and states are satisfied. if ce or oe access times are not met, valid data will be available at the latter of chip enable access (t cea ) or at output enable access time (t oea ). the state of the data input/output pins (dq) is controlled by ce and oe . if the outputs are activated before t aa , the data lines are driven to an intermediate state until t aa . if the address inputs are changed while ce and oe remain valid, output data will remain valid for output data hold time (t oh ) but will then go indeterminate until the next address access. writing data to ram or clock the ds1642 is in the write mode whenever we and ce are in their active state. the start of a write is referenced to the latter occurring transition of we or ce . the addresses must be held valid throughout the cycle. ce or we must return inactive for a minimum of t wr prior to the initiation of another read or write cycle. data in must be valid t ds prior to the end of write and remain valid for t dh afterward. in a typical application, the oe signal will be high during a write cycle. however, oe can be active provided that care is taken with the data bus to avoid bus contention. if oe is low prior to we transitioning low the data bus can become active with read data defined by the address inputs. a low transition on we will then disable the outputs t wez after we goes active. data retention mode when v cc is within nominal limits (v cc > 4.5v) the ds1642 can be accessed as described above by read or write cycles. however, when v cc is below the power-fail point v pf (point at which write protection occurs) the internal clock registers and ram is blocked from access. this is accomplished internally by inhibiting access via the ce signal. when v cc falls below the level of the internal battery supply, power input is switched from the v cc pin to the internal battery and cloc k activity, ram, and clock data are maintained from the battery until v cc is returned to nominal level. battery longevity the ds1642 has a lithium power source that is designed to provide energy for clock activity, and clock and ram data retention when the v cc supply is not present. the capability of this internal power supply is sufficient to power the ds1642 continuously for the lif e of the equipment in which it is installed. for specification purposes, the life expectancy is 10 years at 25 c with the internal clock oscillator running in the absence of v cc power. each ds1642 is shipped from dalla s semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pf , the lithium energy source is enabled for battery backup operation. actual life expectancy of the ds1642 will be much longer than 10 years since no lithium battery energy is consumed when v cc is present.
ds1642 6 of 12 absolute maxi mum ratings voltage range on any pin relative to ground?????????????????..-0.3v to +7.0v operating temperature range?????????????????...0 c to +70c (noncondensing) storage temperature range????????????????????????...-20c to +70c soldering temperature (edip, leads)??????????????..+260 c for 10 seconds (note 7) this is a stress rating only and functional ope ration of the device at these or any ot her conditions above those indicated in t he operation sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc oper ating conditions parameter symbol min typ max units notes logic 1 voltage (all inputs) v ih 2.2 v cc + 0.3 v 1 logic 0 voltage (all inputs) v il -0.3 0.8 v 1 dc electrical characteristics parameter symbol min typ max units notes active supply current i cc 15 50 ma 2, 3 ttl standby current ( ce = v ih ) i cc1 1 3 ma 2, 3 cmos standby current ( ce < v cc - 0.2v) i cc2 1 3 ma 2, 3 input leakage current (any input) i il -1 +1 a i/o leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = -1.0ma) v oh 2.4 1 output logic 0 voltage (i out = +2.1ma) v ol 0.4 1 write protection voltage v pf 4.25 4.37 4.50 v 1
ds1642 7 of 12 ac characteristics?read cycle 70ns access 100ns access parameter symbol min max min max units notes read cycle time t rc 70 100 ns address access time t aa 70 100 ns ce to dq low-z t cel 5 5 ns ce access time t cea 70 100 ns ce data off time t cez 25 35 ns oe to dq low-z t oel 5 5 ns oe access time t oea 35 55 ns oe data off time t oez 25 35 ns output hold from address t oh 5 5 ns read cycle timing diagram
ds1642 8 of 12 ac characteristics?write cycle (v cc = 5.0v 10, t a = 0c to 70c.) 70ns access 100ns access parameter symbol min max min max units notes write cycle time t wc 70 100 ns address setup time t as 0 0 ns we pulse width t wew 50 70 ns ce pulse width t cew 60 75 ns data setup time t ds 30 40 ns data hold time t dh 0 0 ns address hold time t ah 5 5 ns we data off time t wez 25 35 ns write recovery time t wr 5 5 ns
ds1642 9 of 12 write cycle timing diagram?write-enable controlled write cycle timing diagram?chip-enable controlled
ds1642 10 of 12 power-up/power-down ac characteristics (t a = 0c to +70c) parameter symbol min typ max units notes ce or we at v ih before power-down t pd 0 s v cc fall time: v pf (max) to v pf (min) t f 300 s v cc fall time: v pf (min) to v bat t fb 10 s v cc rise time: v pf (min) to v pf (max) t r 0 s power-up recover time t rec 35 ms expected data retention time (oscillator on) t dr 10 years 4, 5 power-up/power-down waveform timing capacitance (t a = +25c) parameter symbol min typ max units notes capacitance on all pins (except dq) c in 7 pf capacitance on dq pins c o 10 pf
ds1642 11 of 12 ac test conditions output load: 100pf + 1ttl gate input pulse levels: 0.0 to 3.0v timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5ns notes: 1) voltages are referenced to ground. 2) typical values are at 25 c and nominal supplies. 3) outputs are open. 4) data retention time is at 25 c. 5) each ds1642 has a built-in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as a cumulative time in the absence of v cc starting from the time power is first applied by the user. 6) real-time clock modules can be successfully processed thro ugh conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post-solder cleaning with water washin g techniques is acceptable, provided that ultrasonic vibration is not used to prevent damage to the crystal.
ds1642 12 of 12 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products ? printed usa the maxim logo is a registered trademark of maxim integrated produ cts, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. package information (the package drawing(s) in this data s heet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) ds1642 24-pin package pkg 24-pin dim. min max a in. mm 1.270 37.34 1.290 37.85 b in. mm 0.675 17.15 0.700 17.78 c in. mm 0.315 8.00 0.335 78.51 d in. mm 0.075 1.91 0.105 2.67 e in. mm 0.015 0.38 0.030 0.76 f in. mm 0.140 3.56 0.180 4.57 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.590 14.99 0.630 16.00 j in. mm 0.010 0.25 0.018 0.45 k in. mm 0.015 0.43 0.025 0.58
english ? ???? ? ??? ? ??? what's new products solutions design appnotes support buy company members ds1642 part number table notes: see the ds1642 quickview data sheet for further information on this product family or download the ds1642 full data sheet (pdf, 704kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming conventions . 4. * some packages have variations, listed on the drawing. "pkgcode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds1642-85+ mod;24 pin;600 dwg: 56-g0002-001a (pdf) use pkgcode/variation: mdf24+1 * 0c to +70c rohs/lead-free: yes materials analysis ds1642-100 mod;24 pin;600 dwg: 56-g0002-001a (pdf) use pkgcode/variation: mdf24-1 * 0c to +70c rohs/lead-free: no materials analysis ds1642-100+ mod;24 pin;600 dwg: 56-g0002-001a (pdf) use pkgcode/variation: mdf24+1 * 0c to +70c rohs/lead-free: yes materials analysis
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